AMD Addresses Controversy: RDNA 3 Shader Pre-Fetching Works Fine

(Image credit: AMD)

Reports that AMD’s RDNA 3 GPUs have a broken shader pre-fetch functionality aren’t accurate, according to a statement that AMD issued to Tom’s Hardware:

“Like previous hardware generations, shader pre-fetching is supported on RDNA 3 as per The code in question controls an experimental function which was not targeted for inclusion in these products and will not be enabled in this generation of product. This is a common industry practice to include experimental features to enable exploration and tuning for deployment in a future product generation.” — AMD Spokesperson to Tom’s Hardware.

AMD’s statement comes on the heels of media reports that the recently launched Navi31 silicon in the RDNA 3 graphics cards have ‘non-working shader pre-fetch hardware.’ The source of the speculation, @Kepler_L2, cited code from the Mesa3D drivers that appeared to indicate the shader pre-fetch doesn’t work for some GPUs with the A0 revision of the silicon (CHIP_GFZ1100, CHIP_GFX1102, and CHIP_GFX110).

However, AMD’s statement says that the code cited by Kepler_L2 pertained to an experimental function that wasn’t intended for the final RDNA 3 products, so it is disabled for now. AMD notes that including experimental features in new silicon is a fairly common practice, which is accurate — we have often seen this approach used with other types of processors, like CPUs. For instance, AMD shipped an entire generation of Ryzen products with the TSVs needed to enable 3D V-Cache, but didn’t use the functionality until third-gen Ryzen. Likewise, Intel often adds features that might not make it into the final product, with its DLVR functionality being a recent example.

Naturally, one would assume that if an ‘experimental’ feature works perfectly fine, it would be included in the final product if it didn’t require any additional accommodations (like the additional L3 cache slice needed for 3D V-Cache). That means the line between an ‘experimental’ or ‘nice to have but not critical or needed to hit targets’ feature could be a bit blurry. In either case, AMD says that the pre-fetch mechanism works on RDNA 3 as intended.

The other elephant in the room is AMD’s use of an A0 stepping of the RDNA 3 silicon, which means this is the first physically-unrevised version of the chip. This has led to claims that AMD is shipping ‘unfinished silicon,’ but that type of speculation doesn’t hold water.

AMD didn’t respond to our queries on whether or not it used A0 silicon for the first wave of RDNA 3 CPUs, but industry sources tell us that the company does use A0 silicon. In fact, we’re told the company launched with A0-revision silicon for almost all of the 6000 series and most of the 5000 series. This is not indicative of an ‘unfinished product.’ The goal of all design teams is to nail the design on the first spin with working, shippable silicon. Nvidia, for instance, often ships A0 stepping silicon, too.

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